Jul 19, 2017 8:46:00 AM
Topics: Electronic Components
Jul 12, 2017 9:08:00 AM
As embedded intelligence is finding its way into ever more areas of our lives, fields ranging from autonomous driving to personalized medicine are generating huge amounts of data. But just as the flood of data is reaching massive proportions, the ability of computer chips to process it into useful information is stalling.
The Team: Researchers at Stanford University and MIT have built a new chip to overcome this hurdle. The team is made up of; Max Shulaker, an assistant professor of electrical engineering and computer science at MIT, H.S. Philip Wong, Subhasish Mitra, professors of electrical engineering and computer science at Stanford. The team also included professors Roger Howe and Krishna Saraswat, also from Stanford.
Computers today are comprised of different chips cobbled together. There is a chip for computing and a separate chip for data storage, and the connections between the two are limited. As applications analyze increasingly massive volumes of data, the limited rate at which data can be moved between different chips is creating a critical communication bottleneck. And with limited room on the board, there is not enough room to place them side-by-side. Even worse, the underlying devices; transistors made from silicon, are no longer improving at the historic rate that they have for decades.
The new prototype chip: is a radical change from today’s chips. It uses multiple nanotechnologies, together with a new computer architecture, to reverse both of these trends.
Instead of relying on silicon-based devices, the chip uses carbon nanotubes, which are sheets of 2-D graphene formed into nanocylinders, and resistive random-access memory (RRAM) cells, a type of nonvolatile memory that operates by changing the resistance of a solid dielectric material. The researchers integrated over 1 million RRAM cells and 2 million carbon nanotube field-effect transistors, making the most complex nanoelectronic system ever made with emerging nanotechnologies.
The RRAM and carbon nanotubes are built vertically over one another, making a new, dense 3-D computer architecture with interleaving layers of logic and memory. By inserting ultradense wires between these layers, this 3-D architecture promises to address the communication bottleneck.
3-D integration can address another key consideration in systems: the interconnects within and between chips. The new 3-D computer architecture provides dense and fine-grained integration of computating and data storage, drastically overcoming the bottleneck from moving data between chips. Because of that, the chip is able to store massive amounts of data and perform on-chip processing to transform a data deluge into useful information.
To demonstrate the potential of the technology: the researchers took advantage of the ability of carbon nanotubes to also act as sensors. On the top layer of the chip they placed over 1 million carbon nanotube-based sensors, which they used to detect and classify ambient gases.
Due to the layering of sensing, data storage, and computing, the chip was able to measure each of the sensors in parallel, and then write directly into its memory, generating huge bandwidth.
Three-dimensional integration: is the most promising approach to allow an increasing number of devices to be integrated per unit volume.
The team is working to improve the underlying nanotechnologies, while exploring the new 3-D computer architecture. The next step is working with Massachusetts-based semiconductors company Analog Devices to develop new versions of the system that take advantage of its ability to carry out sensing and data processing on the same chip.
For example, the devices could be used to detect signs of disease by sensing particular compounds in a patient’s breath. This has the potential to be the platform for many revolutionary applications in the future!
Jul 10, 2017 8:35:00 AM
Jul 7, 2017 8:33:00 AM
Jul 6, 2017 9:41:34 AM
Topics: Electronic Components
Jun 27, 2017 8:27:00 AM
Jan 24, 2017 2:34:57 PM
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Nov 30, 2016 4:41:13 PM
Other than a bit of community chatter (much of it contradictory) there is very little easily digestible information on the differences between the Xilinx Flip Chip (FF- LEADED, FFG-LEADFREE) and the Xilinx Lidless Flip Chip (FB-LEADED, FBG-LEADFREE). Xilinx is very good about providing the information needed if you know where to look. We have worked with many OEMs that have used one or the other or both. In this case, you may want to refer to the following Xilinx data sheet and user guide for more details:
Here is a comparison from Avnet showing that the two devices are pin for pin compatible:
Kintex-7 FPGA Device-Package Combinations and Maximum I/Os. Devices in FBG900/FBV900 and FFG900/FFV900 are footprint compatible.
In a nutshell, the better performing FF/FFG should almost always work in place of the FB/FBG, but not vice versa. The lidless chip will often work in place of the FF/FFG, but with limited performance, including reduced max speeds and diminished thermal properties. The FF/FFG enables faster transfer speeds, better thermal properties, and less margin for error. The FB/FBG has a slightly lower initial height but once the thermal interface material (TIM) and heatsink is applied that dimension frequently becomes irrelevant.
The FB/FBG lidless package requires MANY special considerations and here are a few:
1. Component Pick-up Tool Consideration
For automated pick-and-place machines placing lidless flip-chip BGAs onto PCBs, Xilinx recommends using suction cups or soft tips on the nozzles. Failure to do so will cause chipping, scratching, and cracking of the bare die which can render the chip unusable. This may also lead to failures both immediate or later in the field.
2. TIM (Thermal Interface Material)
Lidless Flip Chips require a layer of thermal interface material between the top of the chip and the heatsink. Because the process of applying this material and the plethora of different materials that can be used it creates another variable that exists even inside a homogenous batch of boards. The upgraded FFG (FF) already has the TIM and heat spreader onboard and built to the exacting Xilinx factory specs, eliminating variables and the concerns of damaging or improperly prepping the FPGA.
3. Heat Sink Guidelines for Lidless Flip-Chip (FB/FBG) Packages
Lidless Flip Chip Concerns:
1. Inconsistent or uneven Force applied.
2. TIM with bond line thickness that is not exactly equal.
3. Even slightly off parallel alignment of the heatsink to the top of silicon will damage and/or destroy the chip.
As you can see, improper heatsink placement onto the die will cause damage and render the lidless chip worthless.
Here are some of the upgrade/benefits of the FFG/FF:
1. TIM (Thermal Interface Material) is already resident.
2. Heat spreader lid which has a flat and uniform surface for the attachment of any additional desired heatsink.
3. Superior thermal/heat dissipation properties of the FFG vs the FBG, excerpted here:
Jul 13, 2016 3:59:49 PM
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May 15, 2015 12:35:57 PM
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