Engineers have worked to shrink drone technology, building flying prototypes that are the size of a bumblebee and loaded with even tinier sensors and cameras. They have managed to miniaturize almost every part of a drone, except for the brains of the entire operation — the computer chip.
Standard computer chips for quadcoptors and other similarly sized drones process an enormous amount of streaming data from cameras and sensors, and interpret that data on the fly to autonomously direct a drone’s pitch, speed, and trajectory. To do so, these computers use between 10 and 30 watts of power, supplied by batteries that would weigh down a much smaller, bee-sized drone.
Now, engineers at MIT have taken a first step in designing a computer chip that uses a fraction of the power of larger drone computers and is tailored for a drone as small as a bottlecap. They will present a new methodology and design, which they call Navion.
The team at MIT developed a low-power algorithm, in tandem with pared-down hardware, to create a specialized computer chip.
Traditionally, an algorithm is designed, and you hand it over to a hardware person to figure out how to map the algorithm to hardware, but by designing the hardware and algorithms together, engineers at MIT can achieve more substantial power savings.
The researchers made slight changes to an existing algorithm commonly used to determine a drone’s awareness of its position in space. They then implemented various versions of the algorithm on a field-programmable gate array (FPGA).
A typical FPGA consists of hundreds of thousands of disconnected gates, which researchers can connect in desired patterns to create specialized computing elements. Reducing the number gates with co-design allowed the team to chose an FPGA chip with fewer gates, leading to substantial power savings.
For each version of the algorithm that was implemented on the FPGA chip, the researchers observed the amount of power that the chip consumed as it processed the incoming data and estimated its resulting position in space.
The team’s most efficient design processed images at 20 frames per second and accurately estimated the drone’s orientation in space, while consuming less than 2 watts of power.
The power savings came partly from modifications to the amount of memory stored in the chip. Sze and her colleagues found that they were able to shrink the amount of data that the algorithm needed to process, while still achieving the same outcome. As a result, the chip itself was able to store less data and consume less power.
This summer, the team will mount the FPGA chip onto a drone to test its performance in flight. Ultimately, the team plans to implement the optimized algorithm on an application-specific integrated circuits, or ASIC, a more specialized hardware platform that allows engineers to design specific types of gates, directly onto the chip.
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